The present invention relates to a clock extraction circuit. More particularly, the present invention relates to a clock extraction circuit, suitable for monolithic integration fabrication, for use in a fiber optical receiver, and which utilizes a nested phase-locked loop for clock regeneration and a frequency-locked loop for a differentiation network.
One known technique of transmitting digital information is with a nonreturn-to-zero coded (NRZ coded) data stream in which a binary "1" is represented by one bit time at the 1, or high, level and a binary "0" is represented by one bit time at the 0, or low, level. This NRZ coding scheme permits placing about twice as much data on the data stream as can be provided with a return-to-zero code, in which a binary 0 is represented by one bit time at the 0 level, and a binary 1 is pulsed in such a way that it reaches the 1 level for only half a bit time. A return-to-zero coded signal therefore returns to 0 (or remains at 0) after each bit of data.
Communications over fiber optic channels often require a receiver to extract a clock signal from an NRZ coded data stream for retiming purposes. Of course, for accurate data transmission it is important to maximize the reliability and precision of the clock extraction circuit.
Ideally, a practical clock extraction circuit should be suitable for monolithic integration with bipolar technology. To minimize production costs, the design of the clock extraction circuit should guarantee high level performance without production adjustments. Additionally, the clock extraction circuit should be independent of absolute device tolerances.
It is a primary object of the present invention to provide a reliable and accurate clock extraction circuit for use in a receiver of NRZ encoded data. It is a further object of the present invention to provide a clock extraction circuit suitable for integration in a bipolar device and which is insensitive to absolute device tolerances.